The present invention relates to nonvolatile memory devices. Even more particularly, the present invention relates to flash memory utilizing periphery and core stacks.
Memory devices such as flash memory or electrically erasable programmable read only memory (EEPROM) are known. U.S. Pat. No. 5,656,513 to Wang et al. and U.S. Pat. No. 5,693,972 to Liu disclose prior art flash memory devices. FIG. 1 is a cross sectional view of an incomplete flash memory structure 10, known in the prior art. Shown, as parts of the flash memory structure 10, are a substrate 12, a plurality of core stacks 16 mounted on the substrate 12 in a row forming a word line, and a periphery stack 14 associated with the word line of the core stacks mounted on the substrate 12 spaced apart from the core stacks 16.
A first oxide layer 18 forms a first layer of the periphery stack 14 and the core stacks 16, where the first oxide layer 18 has a first side adjacent to the substrate 12 and a second side opposite from the first side. The first oxide layer 18 for the periphery stack 14 is a gate oxide layer, and the first oxide layer 18 for the plurality of core stacks 16 are tunnel oxide layers. A first polysilicon layer 20 forms a second layer of the core stacks 16, where the first polysilicon layer 20 has a first side adjacent to the second side of the first oxide layer 18 and a second side opposite from the first side of the first polysilicon layer 20. An interpoly dielectric layer 22 forms a third layer of the core stacks 16, where the interpoly dielectric layer 22 has a first side adjacent to the second side of the first polysilicon layer 20 and a second side opposite from the first side of the interpoly dielectric layer 22. A second polysilicon layer 24 forms a second layer of the periphery stack 14 and a fourth layer of the core stacks 16. A silicide layer 26 forms a third layer for the periphery stack 14 and a fifth layer for the core stacks 16. A third polysilicon layer 28 forms a fourth layer of the periphery stack 14 and a sixth layer of the core stacks 16. An antireflective coating (ARC) 29 forms a fifth layer of the periphery stack 14 and a seventh layer of the core stacks 16.
A protective oxide layer 31 is placed over the periphery stack 14, the core stacks 16 and the uncovered surface of the substrate 12, as shown in FIG. 2, in accordance with the related art. A first high temperature oxidation oxide (insulating) layer 32 is placed over the protective oxide layer 31. A first resist mask 34 is placed over parts of the first insulating layer 32 to cover the periphery stack 14 and parts of the core stacks 16 and the drain area.
The parts of the first insulating layer 32 not covered by the first resist mask 34 are etched partially away to create self aligned source spacers 36, as shown in FIG. 3, in accordance with the related art. The flash memory structure 10 is subjected to a deep source implant to form deep source regions 37 for the core stacks in the substrate 12. The first resist mask 34 is then stripped away and a second insulating layer 39 is placed over the first insulating layer 32, self aligned source spacers 36, and the uncovered parts of the core stacks 16 and substrate 12 surface, as shown in FIG. 4, in accordance with the related art.
The second insulating layer 39 is etched away to form source/drain spacers 40, as shown in FIG. 5, in accordance with the related art. The flash memory structure is subjected to a shallow dopant implant to create shallow more highly concentrated drain regions 42 and source regions 43. A third insulating layer 45 is placed over the self aligned source and source/drain spacers 36, 40, and the uncovered parts of the core stacks 16, periphery stack 14 and substrate 12 surface. An intermetallic dielectric layer (IDL) 46 is placed over the third insulating layer 45. A trench is etched into the intermetallic dielectric layer (IDL) 46 and is filled to create a tungsten plug 48 electrically connected to a drain region 42 of a core stack 16.
Problems in the manufacture of flash memory devices according to the above mentioned process may occur, because etching after the core stacks 16 have been formed may damage the core stacks 16. In addition, process induced charging, caused by processes such as plasma deposition, etching, and chemical mechanical polishing, creates ions which may damage the core stacks 16 by way of trapped charges moving between the tungsten plug 48 and the core stacks through the source/drain spacers 40.
Accordingly, the foregoing related art problems are solved by the present invention in producing a flash memory device on a substrate by a method comprising the steps of: forming a plurality of core stacks on the substrate; forming at least one periphery stack on the substrate; forming an insulating layer over the core stacks, the periphery stack, and the substrate; placing a resist mask over part of the insulating layer; subjecting the resist mask and substrate to a first dopant implantation, wherein the first dopant implantation has sufficient energy to pass dopant through the insulating layer, but does not have enough energy to pass the dopant through the resist layer and the insulating layer, and wherein the dopant passes through a part of the insulating layer not covered with the resist mask into the substrate to form deep source regions in the substrate; stripping away the resist mask; and subjecting the substrate to a second dopant implantation, wherein the second dopant implantation has sufficient energy to pass dopant through the insulating layer, and wherein the dopant passes through the insulating layer into the substrate to form source regions and drain regions. Advantages of the present invention include but are not limited to providing a flash memory device having reduced and even eliminated damage to its core and periphery stacks as well as having reduced current leakage between the plugs and the stacks. Other features of the present invention are disclosed or apparent in the section entitled: xe2x80x9cDETAILED DESCRIPTION OF THE INVENTION.xe2x80x9d